What a Decoupling Capacitor Actually Does

The schematic shows a 100 nF capacitor across VDD and GND, right next to the chip. The layout places it 35 mm away, behind two vias and a length of 0.25 mm track.

Electrically those are not the same circuit. At 1 kHz they are indistinguishable. At 100 MHz the second one is barely a decoupling capacitor at all, and the chip is running on whatever the power plane can deliver.

Understanding why is the whole of this course. This lesson covers the mechanism.

Quick answer. A decoupling capacitor is a local reservoir of charge. The device demands current in nanoseconds and the supply, several centimetres away, cannot respond that fast because the wiring has inductance. The capacitor delivers that current from close by and the supply refills it afterwards. Above a few megahertz, what decides whether it works is not its capacitance but the inductance of the loop it sits in.

What problem is a decoupling capacitor solving?

A digital device does not draw constant current. It draws a series of short pulses, synchronised to its clock edges, as internal transistors switch and charge their internal capacitances.

The power supply, several centimetres away, cannot respond that fast. Not because it is a bad supply, but because the wiring between it and the chip has inductance, and inductance is precisely the property that opposes a rapid change in current.

So the chip has a problem: it needs charge in a few nanoseconds, and its supply can only change its output current over microseconds.

The decoupling capacitor solves this by being a local reservoir of charge that is physically close enough to respond in time. The chip draws its transient current from the capacitor; the supply refills the capacitor slowly afterwards.

Everything else in this course follows from one question: how close is "close enough", and what does "close" actually mean electrically?

Why distance turns into voltage error

Take a simple case. A device switches and demands an extra 0.5 A, and it does so in 2 ns.

The loop that delivers that current — out of the capacitor, along the track, through the via, into the pin, back through ground — has some inductance. Call it L. The voltage developed across an inductance by a changing current is:

V = L × (dI/dt)

With dI/dt = 0.5 A / 2 ns = 250 000 000 A/s, or 2.5 × 10⁸ A/s:

Worked example, chosen to be representative rather than universal. Your dI/dt depends entirely on your device and what it is doing.

Look at what that table says. On a 3.3 V rail, a 5 nH loop costs more than a third of the supply voltage during the transient. A 10 nH loop costs more than the rail can afford at all — the chip browns out, and no amount of extra capacitance fixes it, because capacitance was never the limiting factor.

This is the single most important idea in power integrity: past a certain frequency, a decoupling capacitor's usefulness is set by the inductance of the loop it sits in, not by its capacitance.

So is the capacitance irrelevant?

No — it sets the low-frequency end of the behaviour, and it determines how much charge is available before the voltage sags.

A capacitor's impedance falls with frequency as 1/(2πfC), so bigger is better, up to a point. Its parasitic series inductance (ESL) has impedance 2πfL, which rises with frequency. Somewhere between the two, the capacitor's impedance reaches a minimum and then starts climbing again.

That crossover is the self-resonant frequency. Below it the part behaves like a capacitor. Above it the same part behaves like an inductor, and adding capacitance does nothing at all.

Analog Devices' tutorial on decoupling describes this crossover as the point where capacitive reactance equals the reactance of the ESL, with the minimum impedance set by the ESR and the high-frequency region governed by the ESL — which is in turn strongly affected by package style. That last clause is worth holding onto: the package is part of the electrical design, not a purchasing detail.

Three things that are commonly assumed and are not true

"More capacitance is always better." Above self-resonance, capacitance has stopped participating. A 10 µF capacitor in a large package can be worse at 200 MHz than a 100 nF part in a small one.

"The capacitor is close because it is next to the pin on the schematic." The schematic has no geometry. Proximity is a layout property and can only be verified in the layout.

"100 nF is the right answer." It is a reasonable default that became a habit. Whether it is right depends on the frequency content of the current your device actually draws, which lesson 6 addresses directly.

What this means for how you work

Two practical consequences follow immediately, and both change how you review a board.

First, you cannot assess decoupling from a schematic. The schematic tells you how many capacitors exist and their values. It cannot tell you whether any of them will work, because the thing that decides is the physical loop, which only exists in the layout.

Second, the relevant question is not "how many" but "how short". A single well-placed capacitor with a 1 nH loop outperforms four capacitors sharing a long path to a distant plane. This is why the rest of this course spends more time on geometry than on component selection.

What comes next

Lesson 2 looks at the transient current demand itself: how to estimate what your device actually draws and over what timescale, because that number sets everything downstream.

Lesson 3 then takes loop inductance apart — what contributes to it, roughly how much each part contributes, and which of those you can actually control.

A note on numbers throughout this course: where a specific value appears, it is tied to a stated context. Your device's datasheet takes precedence over any general rule given here, including every rule in this course. Silicon vendors characterise their own parts, and when their guidance and a general principle disagree, the vendor measured and the principle did not.

Sources and further reading

Analog Devices — MT-101: Decoupling Techniques Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis