The Transient Current Demand of a Digital Device

Before you can decide what decoupling a device needs, you need a number: how much current does it demand, and over what time?

Most datasheets will not tell you directly. They give you an average supply current, sometimes a maximum, and almost never a dI/dt. So this lesson is about producing a defensible estimate from what you do have — and about knowing how rough that estimate is.

Quick answer. The average supply current on the datasheet is the wrong number: decoupling has to feed the peaks, not the average. Estimate the peak from the output loads with I = C × V / t_rise, times the number of lines switching together. That peak and the edge time give the inductance budget: L_max = ΔV × t / ΔI. In most digital designs the capacitance is ample and the inductance is marginal.

Why average current is the wrong number

A microcontroller specified at 40 mA does not draw 40 mA continuously. It draws close to zero between clock edges and a large spike at each one. The 40 mA is the average of a waveform that spends most of its time near the bottom and briefly visits the top.

Decoupling has to supply the top, not the average.

The ratio between peak and average is not small. For a synchronous digital device, instantaneous current during a switching edge can be several times the average, and the figure grows with how much of the chip switches at once — which is why the worst case is usually a bus driving all its outputs in the same direction on the same edge.

Three ways to estimate, in increasing order of effort

From the output loads. This is the estimate you can always make, and for I/O-dominated designs it is usually the dominant term.

Every output pin that switches has to charge whatever capacitance it drives. The charge required is Q = C × V, and if that happens over the output's rise time, the average current during the edge is I = C × V / t_rise.

Worked example. A device drives a 16-bit bus. Each line sees roughly 15 pF of trace and input capacitance. The rail is 3.3 V and the outputs have a 2 ns rise time.

Per line: I = 15 pF × 3.3 V / 2 ns = 24.75 mA

All sixteen switching together: roughly 0.4 A, lasting about 2 ns.

That is a real, defensible figure derived from quantities you can look up, and it is the one most people never calculate.

From the core, using the datasheet's dynamic current. Many datasheets give a current-per-MHz figure for the core. Multiply by the clock to get the average core current, then assume the switching concentrates into a fraction of each clock period. The fraction is a guess, so treat this as an order-of-magnitude figure rather than a specification.

From measurement. Put a small shunt in the supply, or a current probe around a wire, and look at the transient on a scope. This is the only method that produces a trustworthy number, and lesson 10 of the Switching Power course covers doing it without the measurement setup inventing its own noise.

Turning current into a decoupling requirement

Once you have a peak current and a rise time, you have both inputs to the calculation that matters.

Suppose you accept a maximum transient droop on the rail. For a 3.3 V device, a common starting point is a few per cent — but check the datasheet, because the device's own supply tolerance is the real limit and it varies widely.

With a target droop ΔV, a peak current step ΔI and an edge time t:

L_max = ΔV × t / ΔI

Using the bus example above, with ΔV = 100 mV allowed:

L_max = 0.1 V × 2 ns / 0.4 A = 0.5 nH

Half a nanohenry for the entire loop. That is a demanding number, and it tells you something useful immediately: this requirement cannot be met by choosing a better capacitor. It can only be met by geometry — short, wide, closely spaced, few vias — which is what lessons 3 to 5 are about.

The same calculation with a slower edge is much kinder. At 10 ns rise time the budget becomes 2.5 nH, which is achievable with ordinary care. This is the clearest argument for not specifying faster edges than you need: edge rate is a power integrity cost, not just an EMI cost.

How the charge requirement sets the capacitance

Inductance sets the high-frequency behaviour. Capacitance has to cover the charge.

The charge delivered during the transient is roughly Q = I × t. For the example: 0.4 A × 2 ns = 0.8 nC.

To supply that charge while dropping no more than ΔV:

C_min = Q / ΔV = 0.8 nC / 0.1 V = 8 nF

Eight nanofarads. A single 100 nF capacitor has more than ten times the charge needed.

That result is worth sitting with, because it explains something that confuses a lot of engineers: in most digital designs the capacitance is comfortably sufficient and the inductance is marginal. When decoupling fails, it is almost never because there was not enough charge available. It is because the charge could not get there fast enough.

What to write down

Whatever you estimate, record it next to the design. The numbers that matter are:

• [ ] Peak transient current, and where the estimate came from
• [ ] Edge time used
• [ ] Allowed droop, and whether it came from the datasheet or from judgement
• [ ] Resulting maximum loop inductance
• [ ] Resulting minimum capacitance

Six months later, when someone asks whether the board can run at a higher clock, this is the note that answers the question in ten minutes instead of a day.

What comes next

You now have a loop inductance budget. Lesson 3 takes that budget and spends it: what the loop is actually made of, and roughly how many nanohenries each part costs.

Every number here is an estimate from a worked example. Use your device's datasheet for its supply tolerance and its dynamic current figures, and treat a measured transient as authoritative over any calculation.

Sources and further reading

Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis Analog Devices — MT-101: Decoupling Techniques