Loop Inductance: The Number That Decides Everything
Where the nanohenries come from, and which of them you control.
- Lesson 3 of 10
- Intermediate
Lesson 2 ended with a budget: half a nanohenry for the whole loop, in a demanding case. This lesson is about where nanohenries come from, so you know what you are spending them on.
What the loop actually is
The loop is not "the distance from the capacitor to the chip". It is the complete closed path that the transient current travels:
- out of the capacitor's terminal
- along the track or plane to the device's power pin
- through the device
- out of its ground pin
- back through ground to the capacitor's other terminal
Including, at every layer change, the vias.
Two things follow from drawing it as a closed loop. The first is that the return path matters exactly as much as the outbound path — a short track to the pin with a long return route around a plane gap is a long loop. The second is that the loop encloses an area, and inductance scales with that area far more than with the length of either conductor.
That is the single most useful mental model in this subject: you are not shortening a wire, you are shrinking an area.
Where the nanohenries go
| Contributor | Typical order | Can you control it? |
|---|---|---|
| Capacitor's own ESL (0402 ceramic) | a few hundred pH | Yes — package choice |
| Capacitor's own ESL (0805 ceramic) | roughly double an 0402 | Yes — package choice |
| Pad and fanout track to the via | 0.1–1 nH, length-dependent | Yes — this is the big one |
| A via through a thin stackup | a few hundred pH | Partly — stackup and via count |
| A via through a thick board | over 1 nH | Partly — stackup |
| Plane spreading inductance | small, but not zero | Partly — plane proximity |
| Device package and bond wires | often 1 nH or more | No |
Orders of magnitude, not specifications. Actual values depend on geometry, stackup and the specific part, and the only way to know yours is to extract them from your own layout.
Two conclusions fall out of this table immediately.
The package contribution is often the floor. If the device's internal inductance is 1 nH, no external work will get the total below 1 nH. When a budget comes out below the package's own contribution, the answer is not better layout — it is a different package, a slower edge, or accepting more droop. Knowing this stops a lot of wasted effort.
The fanout track is where designs are won and lost. It is the one term that routinely varies by a factor of ten between a careful layout and a careless one, and it is entirely under your control.
Why length is not the whole story
Inductance per unit length falls as a conductor gets wider, but slowly — the relationship is roughly logarithmic, not proportional. Doubling the width of a track does not halve its inductance.
What does help substantially is bringing the outbound and return conductors close together. Current flowing one way and its return flowing the other way nearby creates opposing magnetic fields that largely cancel. The closer the two, the more complete the cancellation and the lower the loop inductance.
This is why a signal over a nearby reference plane has far lower loop inductance than the same signal over a distant one, and why plane separation in the stackup is a power integrity parameter rather than a mechanical one. TI's PDN guidance for one of its processor families makes this point directly, recommending that the power and ground plane pair sit near the outer surfaces specifically because it reduces the loop inductance contributed by capacitor mounting, vias and plane spreading.
So the three levers, in the order they usually pay off:
- Shorten the fanout from pad to via.
- Bring the planes closer to the surface the capacitor is on.
- Reduce the enclosed area by keeping outbound and return adjacent.
A worked comparison
The same 100 nF 0402 capacitor, mounted two ways on the same board.
Mounting A. Pads with 2 mm of 0.25 mm track to a via on each side, vias dropping 1.5 mm to the plane pair.
| Term | Estimate |
|---|---|
| Capacitor ESL | 0.4 nH |
| Two fanout tracks | 1.6 nH |
| Two vias | 0.8 nH |
| Total | ≈ 2.8 nH |
Mounting B. Vias placed directly against the pads, no fanout track, plane pair 0.2 mm below the surface.
| Term | Estimate |
|---|---|
| Capacitor ESL | 0.4 nH |
| Fanout | negligible |
| Two vias | 0.2 nH |
| Total | ≈ 0.6 nH |
Estimated figures for a comparison, not measurements. The ratio is the point: the same component, the same board, more than four times the inductance, decided entirely by two millimetres of track and where the planes sit.
Against the 0.5 nH budget from lesson 2, mounting A fails by a factor of five and mounting B is marginal. No change of component gets mounting A to pass.
The question to ask at review
When you look at a decoupling capacitor on a layout, the useful question is not "is it close to the chip?" It is:
Trace the current from this capacitor's positive terminal to the pin, and back from the ground pin to the capacitor's negative terminal. How much area does that loop enclose, and what is the longest segment in it?
If you cannot answer that by looking, the loop is probably larger than you think.
What comes next
Lesson 4 turns this into placement rules: how the loop behaves as you move the capacitor around, why "within X mm" is a misleading way to state the requirement, and what to do when the pitch of a package leaves you nowhere to put anything.
Inductance values here are estimates used to compare two geometries. For real numbers, extract them from your own stackup with a field solver, and treat your device's datasheet as authoritative for its own package contribution.
Sources and further reading
Texas Instruments — SPRABJ7: PDN Analysis Application Report Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis * Analog Devices — MT-101: Decoupling Techniques