Placement: Why Distance Matters and How Much
Why “within X mm” hides the variables that actually decide.
- Lesson 4 of 10
- Intermediate
How close does a decoupling capacitor need to be?
Close enough that the loop inductance stays inside the budget you calculated in lesson 2. That is the whole rule, and it is the only form of the rule that survives contact with a real board.
It is unsatisfying because it does not give you a number. But any answer that does give you a single number — "within 3 mm", "within 10 mm" — is hiding the variables that actually decide: your device's dI/dt, your allowed droop, your stackup, your via geometry and your package. Change any of those and the distance changes with it.
What follows is how to work with that honestly.
Why "within X mm" misleads
Consider two boards. Both place a 100 nF capacitor 3 mm from the device pin.
On the first, the plane pair sits 0.2 mm below the surface and the vias are against the pads. The loop is under a nanohenry, and 3 mm is comfortably close.
On the second, the plane pair sits 1.5 mm down, the capacitor fans out through 0.25 mm track to vias placed 2 mm away, and the return crosses a plane gap. The loop is several nanohenries. The capacitor is the same distance away and is far less effective.
Same number of millimetres. Different circuits. Distance along the surface is a weak proxy for the thing that matters, which is enclosed loop area, and most of that area is usually vertical — down through the stackup and back.
This is why vendor guidance tends to be device-specific rather than general. When TI specifies decoupling for a particular MSP430 part, for instance, it names both the values and a placement within a few millimetres of the pins they serve — but that is guidance for that device, tied to its characterised behaviour, not a law of nature you can carry to a different chip.
Where the datasheet gives you a distance, use the datasheet's number. It was produced by people who measured that part.
A placement order that works
When you cannot measure, place by priority. Nearest position to the pin goes to the capacitor whose job is most distance-sensitive.
- Smallest, lowest-ESL capacitor closest. High-frequency content is the
part that distance destroys fastest. The 100 nF 0402 wins the prime spot over the 10 µF 0805.
- Same side as the device, if the via drop allows. Mounting on the
opposite side can be fine, and is sometimes better, when the plane pair is near that surface — the vertical distance is what counts, not which face the part sits on.
- Bulk capacitance can be further away. It is working at frequencies
where a few extra millimetres of track are electrically invisible.
- Prioritise the noisiest pins. Core supplies and I/O banks that switch
wide buses need the good positions more than a sleepy analog rail.
That ordering matters more than any absolute distance, because it allocates your scarce good positions to the capacitors that can actually use them.
When there is no room
On a fine-pitch BGA there is often nowhere to put a capacitor near the pin at all. This is a real constraint, not a failure of effort, and vendors acknowledge it: TI's own guidance for fine-pitch packages notes that the older rule of one capacitor per power pin becomes nearly impossible below about 1.0 mm pitch, and that practical placement and value selection has to replace it.
What to do instead, roughly in order of cost:
Mount on the opposite face, directly under the pin field. The via drop is vertical and short. This is usually the first and best answer.
Use the plane pair itself. Closely spaced power and ground planes form a capacitor with essentially no mounting inductance. It is small in value but works at frequencies where no discrete part does. Bringing the plane pair closer together is often the highest-value change available at stackup time.
Accept fewer, better-mounted capacitors. Four capacitors with excellent mounting beat twelve with poor mounting. The count is not the figure of merit.
Reduce the demand. Slower edge rates, lower drive strength on wide buses, staggered switching. This is a firmware and pin-configuration lever that hardware engineers often forget they have.
A decision table
| Situation | What usually dominates | First thing to change |
|---|---|---|
| Thick board, planes deep | Via inductance | Move plane pair toward the surface |
| Capacitor fanned out on track | Fanout inductance | Via directly at the pad |
| Fine-pitch BGA, no surface room | Access to the pin field | Mount on the opposite face |
| Many capacitors, still droops | Shared vias or shared path | Give each capacitor its own vias |
| Droop only at high clock | Package inductance floor | Slower edges, or a different package |
| Analog rail picking up digital noise | Shared return path | Separate the return, not the plane |
Starting points for diagnosis, not a substitute for measuring your own board.
The mistake that looks like diligence
Sprinkling capacitors. A board with forty 100 nF parts, all fanned out on 0.5 mm of track to shared vias, has spent forty placements and forty purchasing lines to build forty mediocre loops in parallel.
Parallel loops do help — inductances in parallel divide — but they divide a large number. Ten 3 nH loops in parallel give 0.3 nH only if they are truly independent, and capacitors sharing a via are not independent at all. TI's PDN layout guidance for one of its processor platforms is explicit about this, recommending roughly one via per pin where possible and specifically advising against sharing vias among multiple capacitors.
The engineering move is to make a few loops excellent, not many loops adequate.
What comes next
Lesson 5 goes down to the millimetre: the actual pad and via patterns that keep mounting inductance low, with the geometries that work and the common ones that quietly do not.
Distances and inductance figures in this lesson are illustrative. Your device's datasheet takes precedence, and where it specifies a placement distance or a capacitor value, that number was characterised against that silicon and this lesson was not.
Sources and further reading
Texas Instruments — SPRABV2: BGA PCB Design and Decoupling Texas Instruments — SPRACE6: PDN Analysis and Layout Guidance * Analog Devices — MT-101: Decoupling Techniques