Via and Pad Patterns That Keep Inductance Low
Vias, pads, and the thermal relief that quietly costs you half a nanohenry.
- Lesson 5 of 10
- Intermediate
Two millimetres of 0.25 mm track costs roughly as much inductance as the capacitor itself. That is the scale this lesson works at: the geometry between the pad and the plane, where most mounting inductance is created and where it is cheapest to remove.
The patterns, worst to best
Fanout to a shared via. Both capacitors route out to one via each side. The loop includes both fanout tracks, and the two capacitors are no longer independent — they share the via's inductance, so paralleling them buys much less than it appears to.
Fanout to dedicated vias. Each capacitor gets its own vias, reached by a short track. Better, because the capacitors are independent, but the fanout track is still in the loop.
Vias at the pad ends. The via sits immediately at the outer end of each pad. The fanout term nearly disappears. This is the standard good practice and is achievable on most boards.
Vias beside the pads. Vias placed to the sides of the pads rather than in line, which shortens the loop further by narrowing the area between outbound and return.
Via-in-pad. The via is inside the pad itself. Lowest inductance available with discrete parts, at the cost of a filled-and-plated process step, which is a real manufacturing decision and not free.
The jump from the first to the third is large and usually free. The jump from the third to the fifth is smaller and costs money. Most designs should take the first jump and only argue about the second when the budget demands it.
Why via placement changes the loop so much
The loop is an area. With the vias in line past the ends of the pads, the current goes out along the component, down a via, back through the plane, and up the other via — the enclosed area is roughly the component length times the depth to the plane.
Move the two vias to the sides of the component instead, and the horizontal separation shrinks while the vertical depth stays the same. Smaller area, less inductance, same component, same layer count.
This is also why the depth to the plane matters as much as anything you do on the surface. On a board where the plane pair is 1.5 mm down, the vertical part of the loop dominates and surface optimisation has limited returns. Fix the stackup first; it is a bigger lever than any pad geometry.
Rules that hold up
- [ ] One pair of vias per capacitor. Do not share vias between capacitors.
- [ ] Vias as close to the pads as the design rules permit.
- [ ] Shortest possible connection from pad to via, ideally none.
- [ ] Both vias reach the plane pair they are decoupling — the power via to
the power plane, the ground via to the ground plane it returns through.
- [ ] Where room exists, two vias per terminal rather than one. Vias in
parallel divide inductance.
- [ ] No thermal relief spokes on decoupling vias. Spokes exist to help
soldering and they add inductance exactly where you cannot afford it.
- [ ] Keep the power and ground vias close to each other, not at opposite ends
of the part.
The thermal relief item catches people out. A spoked connection can add a meaningful fraction of a nanohenry, and on a plane that is already being reflow-soldered as a whole, the spokes are often solving a problem the process does not have. Check with your fabricator rather than leaving the library default in place.
The mounting comparison, numerically
The same 0402 capacitor on the same 4-layer board, plane pair 0.8 mm below the surface.
| Mounting | Fanout | Via count | Estimated loop |
|---|---|---|---|
| 1.5 mm track to shared vias | 1.5 mm each side | 2 shared | ~3.0 nH |
| 1.5 mm track to own vias | 1.5 mm each side | 2 | ~2.4 nH |
| Vias at pad ends | none | 2 | ~1.2 nH |
| Vias beside pads | none | 2 | ~1.0 nH |
| Two vias per terminal, beside pads | none | 4 | ~0.8 nH |
Estimates for comparison on one stackup. The absolute values will differ on yours; the ordering will not.
Note where the big win is. Removing 1.5 mm of fanout halves the loop. Doubling the via count after that buys 20 %. Spend your attention accordingly.
What this looks like in a library
Most of this is won or lost in the footprint library, not in each layout.
If your 0402 decoupling footprint carries vias at the pad ends as part of the footprint, every engineer who places it gets good mounting by default, and good mounting stops depending on whether anyone remembered. If the footprint is bare pads, every placement is a fresh opportunity to get it wrong.
Making this a library property rather than a layout habit is the single single change with the greatest effect available to a team, and it costs one afternoon.
What comes next
Lesson 6 moves from geometry back to the component: how to choose values with reasoning, and whether the 100 nF default deserves its position.
Inductance figures are estimates for one stackup, used to show relative effect. Confirm via and pad geometry against your fabricator's capabilities before committing, particularly for via-in-pad, which requires a specific process.
Sources and further reading
Texas Instruments — SPRACE6: PDN Analysis and Layout Guidance Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis