Choosing Values: The 100 nF Habit Examined

Open almost any schematic and you will find 100 nF next to every power pin. It is the most reproduced value in electronics, and most of the people placing it could not say why that number rather than 47 nF or 220 nF.

It is not a bad default. It is a default that stopped being examined. This lesson examines it.

Quick answer. 100 nF is a reasonable default, not an answer. Three things set the value: the charge to be delivered (usually small), the highest frequency at which you need low impedance, and the package ESL. Once mounting inductance dominates, increasing capacitance lowers the self-resonant frequency and makes the part worse at high frequency. Choose the package before the value.

Where the habit came from

100 nF in a small ceramic package sits at a useful compromise. Its self-resonant frequency lands in the tens of megahertz for typical mounting, which covers the switching content of a great many digital devices. It is cheap, universally stocked in every package size, and available in temperature characteristics that do not collapse under DC bias.

So the habit is well founded. The problem is that the reasoning behind it is rarely transferred along with the value, which means it gets applied unchanged to cases it does not fit.

What actually sets the value

Three questions, in this order.

What charge must be delivered? From lesson 2: C_min = Q / ΔV. For most digital loads this comes out small — single-digit nanofarads — which is why capacitance is rarely the binding constraint.

At what frequency must the impedance be low? This is the real question. The capacitor is only useful below its self-resonant frequency, and the self-resonant frequency depends on both the capacitance and the total inductance of the part plus its mounting:

f_sr = 1 / (2π √(L × C))

Here is the consequence that surprises people. Once mounting inductance dominates, increasing capacitance lowers the self-resonant frequency and makes the part less useful at high frequency, while buying charge you already had enough of.

With a 1.5 nH total loop:

Calculated for one assumed loop inductance, to show the trend. Real parts vary with package and mounting, and manufacturers publish impedance curves for their own parts — use those when precision matters.

What does the package cost you? A larger case size has more ESL. A 10 µF in 1206 may have several times the ESL of a 100 nF in 0402, which pushes its self-resonance down twice over — once for the capacitance, once for the inductance.

So when is 100 nF wrong?

When the device switches faster than the part can follow. A capacitor resonant at 13 MHz contributes little at 200 MHz. If your device has sub-nanosecond edges, you need lower inductance, which usually means a smaller package and better mounting rather than a different value.

When the load is mostly low-frequency. A linear regulator feeding an op-amp does not need 100 nF of high-frequency decoupling as much as it needs bulk capacitance and a stable output. Check the regulator's own stability requirements first — many LDOs specify both a minimum capacitance and an ESR range, and violating those causes oscillation, which is a worse problem than imperfect decoupling.

When DC bias eats it. A 100 nF X7R in a small case at 80 % of its rated voltage may deliver a fraction of its nominal value. If you need 100 nF, you have to pick a part that still has 100 nF under your actual bias — which is a C02 topic, and the single most common silent error in capacitor selection.

When the datasheet says otherwise. Vendors characterise their own devices and frequently specify both values and placement. TI's guidance for one MSP430 family, for instance, calls for a 10 µF and a 100 nF low-ESR ceramic on the supply pins, placed within a few millimetres. That is a measured recommendation for that part. Follow it over any general rule, including everything in this lesson.

A defensible selection procedure

1. Read the device datasheet's decoupling section. If it specifies values,

start there and stop arguing.

1. Estimate peak transient current and edge time (lesson 2).
2. Compute the charge requirement. Confirm it is comfortably met — it usually

is.

1. Identify the highest frequency at which you need low impedance. Roughly,

0.35 / t_rise gives the knee frequency of an edge.

1. Choose the smallest package you can mount well, because package sets ESL

and ESL sets the upper limit.

1. Pick a capacitance whose self-resonance, *with your mounting inductance

included*, sits at or above that knee.

1. Check the value survives DC bias and temperature at your operating point.
2. Add bulk capacitance separately for the low-frequency end (lesson 7).

Step 5 before step 6 is the part that differs from habit. Most people choose the value first and accept whatever package it comes in. Choosing the package first is usually the better order, because the package decides the ceiling.

What to do with the default

Keep it. A 100 nF 0402 remains a sound default for general digital decoupling, and standardising on one part across a board has real benefits in purchasing and assembly.

What should change is the status of the decision. Write down, once per project, why that value was chosen and what frequency range it covers. Then when a device appears with 500 ps edges, somebody notices that the default no longer reaches, instead of placing it by reflex and debugging it six months later.

What comes next

Lesson 7 deals with the other end: bulk capacitance, mid-frequency parts, and how to divide the frequency range between them without creating the anti-resonance that lesson 8 is about.

Self-resonance figures here are calculated from an assumed loop inductance to illustrate a trend; they are not part specifications. Use the manufacturer's impedance curves for a specific component, and your device's datasheet takes precedence over every recommendation in this lesson.

Sources and further reading

Analog Devices — MT-101: Decoupling Techniques Texas Instruments — SPRABV2: BGA PCB Design and Decoupling