Plane Capacitance and the Power Distribution Network
Target impedance, and how much of it your board actually needs.
- Lesson 9 of 10
- Intermediate
Every lesson so far has looked at one capacitor at a time. A real board has dozens, plus the planes they connect to, plus the regulator feeding them, plus the inductance of everything in between.
Taken together that is the power distribution network, and it has one property worth characterising: its impedance, as seen by the device, across frequency.
Quick answer. Target impedance is
Z = ΔV / ΔI: the droop the device tolerates divided by its current step. The network must stay below that figure at every frequency where the transient has energy, which is the hard part. A board with one microcontroller and slow I/O does not need this analysis; a board with a vendor-published target or tight EMC margin does.
Target impedance in one paragraph
If a device draws a transient current ΔI and can tolerate a supply variation of ΔV, then the PDN must present an impedance no greater than:
Z_target = ΔV / ΔIA device allowed 50 mV of droop while drawing a 2 A transient needs the PDN below 25 mΩ — and it needs that at every frequency where the transient has energy, which is the part that makes it hard.
This is the same arithmetic as lesson 2, reframed. Lesson 2 asked "how much inductance can I afford?" Target impedance asks "what must the whole network look like across the band?" It is the formulation used by processor vendors precisely because it covers the whole frequency range at once rather than a single edge.
Who supplies what, at which frequency
| Frequency | What is actually supplying the current |
|---|---|
| DC to ~1 kHz | The regulator's control loop |
| ~1 kHz to ~1 MHz | Bulk capacitance |
| ~1 MHz to ~50 MHz | Ceramic decoupling |
| ~50 MHz upward | Plane capacitance and the device's own on-die capacitance |
| Beyond that | Nothing you can influence from the board |
Approximate crossovers. Yours shift with regulator bandwidth, capacitor mounting and stackup.
Two observations follow, and both change how you spend effort.
At the high end, the board loses. Above some frequency nothing mounted on the surface can respond in time, and the device is running on its package and die capacitance. That is a silicon property. If you need help there, you need a different device, not a different layout.
At the low end, the regulator matters more than the capacitors. A regulator with poor transient response makes bulk capacitance do work it was not sized for. Reading the regulator's load-transient plot is often more informative than adding another electrolytic.
The capacitor you get for free
A power plane and a ground plane separated by thin dielectric form a parallel plate capacitor across the whole board.
Its capacitance is modest — in the nanofarad range for typical geometry — but it has two properties no discrete part can match: essentially zero mounting inductance, because there is nothing to mount, and it is distributed everywhere rather than at points.
That makes it the dominant element at the top of the usable range, exactly where discrete capacitors have gone inductive. It is also why plane spacing is a power integrity decision. Halving the dielectric thickness between the power and ground planes roughly doubles this capacitance and simultaneously reduces the loop inductance of every capacitor mounted to them.
Few stackup changes improve two things at once. This one does, and it is usually free at the design stage and impossible afterwards.
A review sequence for a whole rail
Rather than checking capacitors one at a time, walk the rail:
- Start at the load. What is the worst transient, and what droop is
allowed? Datasheet first.
- Compute target impedance.
ΔV / ΔI. One number to carry through. - Work outward. For each element — device package, local ceramics, plane
pair, mid capacitance, bulk, regulator — ask which frequency band it covers and whether anything covers the gaps.
- Look for the handover points. Gaps between bands are where unexplained
noise lives, and anti-resonance peaks sit exactly there.
- Check the return path. Everything above assumes the return is as good
as the outbound path. If the ground plane is interrupted, none of it holds.
- Compare against the budget. If the worst band exceeds target
impedance, that is where to spend.
Step 5 is the one most often skipped, and it is covered properly in the PCB Grounding & Return Paths course, because a decoupling network over a fragmented ground is not the network you drew.
How much of this does a small board need?
Not much, and it is worth saying plainly.
If your board runs a microcontroller at 48 MHz with a handful of peripherals, you do not need a PDN impedance plot. You need capacitors in the right places with short loops, which is lessons 3 to 5, and a sanity check against the datasheet.
Target impedance analysis earns its keep when a vendor publishes a target for your device, when you have many rails interacting, or when EMC margin is tight. Below that, the formality costs more than it returns, and the honest advice is to spend the time on geometry instead.
What comes next
Lesson 10 turns everything in this course into a review checklist you can run against a finished layout in about twenty minutes.
Frequency crossovers and capacitance values here are approximate and depend on your stackup, components and regulator. Where a device vendor publishes a target impedance curve for your part, that curve takes precedence over any general guidance in this lesson.
Sources and further reading
Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis Texas Instruments — SPRABJ7: PDN Analysis Application Report * Analog Devices — MT-101: Decoupling Techniques