Anti-Resonance: When Two Capacitors Are Worse Than One
Why mixing values can raise the impedance instead of lowering it.
- Lesson 8 of 10
- Intermediate
You add a 1 µF capacitor next to the existing 100 nF, expecting the impedance to fall everywhere. At most frequencies it does. At one particular frequency it rises — sometimes above what either capacitor gave on its own.
That peak is anti-resonance, and it is the reason "add more capacitors" is not a reliable strategy.
Quick answer. Yes. Between the resonances of two different capacitors, the larger one is already inductive while the smaller is still capacitive: that is a parallel resonant circuit, and its impedance is at a maximum at resonance. Only loop resistance limits the peak, so a pair of low-ESR ceramics makes it worse. For high frequency, repeating one value usually beats a decade ladder.
Why two capacitors can be worse than one
Above its self-resonant frequency, a capacitor is inductive. Below its self-resonant frequency, a capacitor is capacitive.
Put a 1 µF and a 100 nF in parallel and there is a band between their two resonances where the larger part has already gone inductive and the smaller part is still capacitive. In that band you have an inductor in parallel with a capacitor, which is a parallel resonant circuit — and a parallel resonant circuit has maximum impedance at its resonant frequency.
The only thing limiting the height of that peak is the resistance in the loop: the ESR of the parts and the resistance of the mounting. A low-ESR ceramic pair, which is what you reach for to get low impedance, produces a higher anti-resonant peak than a lossier pair would.
This is the uncomfortable part. The same property that makes ceramics good at their resonance makes them bad between resonances.
What it looks like in practice
| Frequency region | 1 µF alone | 100 nF alone | Both together |
|---|---|---|---|
| Below 1 MHz | low | higher | low |
| At 1 µF resonance | lowest | higher | low |
| Between the two | rising, inductive | falling, capacitive | peak |
| At 100 nF resonance | inductive | lowest | low |
| Above both | inductive | inductive | inductive, halved |
Qualitative behaviour. The frequency and height of the peak depend on the actual parts and their mounting inductance, and the only way to know yours is to simulate or measure the assembled PDN.
The peak sits between the two resonances. With a decade between the capacitances, it lands roughly in the middle of that decade — and if your device happens to have significant current content at that frequency, you have built a noise amplifier.
Four ways to handle it
Use fewer distinct values. Several capacitors of the same value in parallel do not anti-resonate with each other. They lower impedance and move the combined resonance, without creating a peak between them. For high-frequency decoupling this is often the better strategy, and it simplifies purchasing at the same time.
Space the values more closely. Closer capacitances put the resonances nearer together, which makes the peak narrower and lower. A 100 nF and a 220 nF anti-resonate much more gently than a 100 nF and a 10 µF.
Accept some loss. A part with slightly higher ESR damps the peak. This is one of the few places in electronics where a worse component gives a better result, and it is why polymer and tantalum parts sometimes outperform ceramics in the mid band despite inferior specifications.
Move the peak somewhere harmless. If you know your load's frequency content, you can place the anti-resonance away from it. This requires knowing the content, which brings you back to lesson 2.
The practical recommendation
For most boards, in order:
- Use one value for high-frequency decoupling, repeated as many times as
the pins and the space allow, mounted as well as possible.
- Add one mid-frequency value if the band needs covering, chosen within
a factor of ten or so of the small parts rather than a hundred.
- Add bulk with some inherent loss — polymer or electrolytic rather than
a large ceramic — which damps rather than sharpens.
That is close to the opposite of the decade-ladder habit from lesson 7, and for high-speed digital boards it is usually the better answer. The ladder assumes the parts cover separate bands cleanly; anti-resonance is the reason they do not.
When it is worth simulating
Honest answer: when the consequences justify it.
A simple board with one microcontroller and slow I/O will almost never be limited by anti-resonance. Build it, and if the rail is quiet, it is quiet.
Simulation earns its cost when you have a processor with a published target impedance, many supply rails, or a product that has to pass EMC with margin. A PDN impedance plot across frequency is standard practice at that level, and vendors of large processors provide target impedance curves specifically so that it can be done. TI's PDN guidance for its Sitara family, for example, covers selecting decoupling capacitors against a target impedance as part of the design flow rather than as an afterthought.
If you are below that threshold, the geometry lessons in this course will serve you better than a simulation would.
What comes next
Lesson 9 steps back from individual capacitors to the whole power distribution network, including the one capacitor you get for free: the plane pair itself.
The behaviour described here is qualitative. Actual anti-resonant frequencies and peak magnitudes depend on your specific parts, mounting and stackup, and are best obtained from manufacturer impedance data or your own PDN simulation.
Sources and further reading
Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis Analog Devices — MT-101: Decoupling Techniques