A Decoupling Review Checklist for a Finished Layout

This is the course condensed into something you can run against a finished layout before it goes out. It takes about twenty minutes on a typical board, and it is deliberately ordered so that the cheapest-to-fix items come first.

Work with the layout open, not the schematic. Most of these questions cannot be answered from a schematic at all, which is the point.

Before you start

• [ ] Device datasheets to hand, open at the power supply section
• [ ] Stackup drawing, with dielectric thicknesses
• [ ] The transient estimate from lesson 2, if one was made

If the third item does not exist, make a rough one now. Reviewing decoupling without any idea of the current demand is guessing with extra steps.

Stackup

• [ ] Is there a solid power/ground plane pair?
• [ ] How far below the surface is it? Under 0.5 mm is comfortable; over

1 mm makes every capacitor worse.

• [ ] Are the power and ground planes adjacent to each other, not separated

by signal layers?

• [ ] Is the dielectric between them as thin as the fabricator allows at no

extra cost?

Stackup problems cannot be fixed by moving capacitors, and they get more expensive to fix the later they are found. This is why they come first.

Per device

For each significant device, and especially the ones with fast edges:

• [ ] Does the datasheet specify decoupling values? Are they what is fitted?
• [ ] Does the datasheet specify a placement distance? Is it met?
• [ ] Is there at least one high-frequency capacitor per power pin group?
• [ ] Is the smallest-package capacitor the closest one?
• [ ] Are analog and digital supplies decoupled separately where the

datasheet asks for it?

Per capacitor

This is where the time goes. For each decoupling capacitor:

• [ ] Can you trace the full loop — out, through the device, back — by

looking at the layout?

• [ ] Does it have its own vias, not shared with another capacitor?
• [ ] Are the vias at the pads, or is there fanout track in the loop?
• [ ] Do the vias actually reach the plane pair being decoupled?
• [ ] Are power and ground vias close together rather than at opposite ends?
• [ ] Any thermal relief spokes on the vias? Remove them.
• [ ] Is the return path to the device unbroken, with no plane gap crossed?

The last item fails more often than the rest combined, and it is invisible unless you look at the plane layer specifically.

Across the board

• [ ] Are there gaps or slots in the ground plane under any decoupling loop?
• [ ] Do any decoupling return paths cross a plane split?
• [ ] Is bulk capacitance near the load that needs it, not near the connector?
• [ ] Does each rail have coverage in every frequency band its load needs?
• [ ] If multiple distinct values are used, are they within about a decade of

each other rather than several?

Sanity checks that catch real errors

• [ ] Capacitor voltage ratings above the rail with derating margin
• [ ] Dielectric appropriate — X7R or better for anything that matters, not

Y5V

• [ ] DC bias derating checked for any capacitance you are relying on
• [ ] Any LDO output capacitors within the regulator's specified capacitance

and ESR window

• [ ] No capacitor placed on the wrong side of a ferrite or filter from the

pin it is meant to decouple

The last one is a classic. A capacitor on the supply side of a ferrite bead is not decoupling the device behind it, and the schematic makes it look correct.

Scoring the review

If you want a crude pass mark, three questions decide most of it:

1. Is the plane pair close to the surface? If not, nothing else fully

compensates.

1. Do the critical capacitors have vias at their pads? If not, this is

the cheapest improvement available.

1. Is the return path intact? If not, fix that before touching anything

else.

A board that passes those three with ordinary components usually works. A board that fails any of them will not be rescued by adding parts.

Record the outcome

Whatever you find, write it down with the design: the transient estimate, the target loop inductance, which capacitors were reviewed, and what was changed.

The next person to open this layout — possibly you, after a year — will otherwise re-derive all of it from scratch, or more likely not bother and assume it was considered.

This is the one place where XKEMA's own subject matter touches this course. It does not help you choose a capacitor or shorten a loop; those are engineering judgements and no tool makes them for you. What it does is keep the reasoning attached to the board revision it applies to, so that a review done once stays findable.

* Hardware documentation

Where to go next

• The PCB Grounding & Return Paths course, which covers the return-path

items here in proper depth.

• The Switching Power course, if the rail in question comes from a buck

converter, because its input loop obeys different rules.

• The Engineering Notes on power problems, for symptom-first diagnosis when a

board is already misbehaving.

This checklist is a review aid, not a specification. Device datasheets and your fabricator's capabilities take precedence over every item on it.

Sources and further reading

Texas Instruments — SPRAC76: Sitara Processor PDN Implementation and Analysis Texas Instruments — SPRACE6: PDN Analysis and Layout Guidance * Analog Devices — MT-101: Decoupling Techniques