Input Bias Current: When Nanoamps Matter
Ten nanoamps into a one-megohm source is ten millivolts of error, nearly seventy times the offset.
- Lesson 6 of 10
- Intermediate
The same amplifier that was accurate to 150 microvolts in the last lesson can be wrong by ten millivolts in the next circuit, with nothing changed about the amplifier. What changed is what is connected to it.
Input bias current is the parameter that makes the source impedance part of the amplifier's specification. Ignore it with a 1 kΩ source and you lose nothing. Ignore it with a 1 MΩ source and it becomes the largest error in the design.
Quick answer. Input bias current is the small DC current each input terminal needs in order to work, from picoamps in CMOS and JFET parts to tens or hundreds of nanoamps in bipolar ones. It produces an error by flowing through whatever resistance it sees, so the voltage error is current times resistance. Input offset current is the difference between the two inputs' bias currents, and it is what remains after you have balanced the resistances.
Why the inputs need current at all
The two input terminals go to transistors, and the kind of transistor decides the answer.
A bipolar input stage needs base current to keep its transistors conducting, so the bias current is substantial, fairly predictable, and relatively stable with temperature because it is tied mainly to the transistor's current gain. Some bipolar parts include internal cancellation circuitry that subtracts most of it, which reduces the bias current while leaving a larger mismatch between the two inputs.
A CMOS or JFET input stage draws almost nothing by comparison, because what flows is reverse leakage across a junction rather than a current the device needs. That leakage is tiny at room temperature and roughly doubles for every 10 °C rise, which is a different and sometimes worse behaviour than the bipolar case.
That last sentence is the one worth keeping. CMOS is not simply better. It is better at 25 °C and gets worse faster.
The error is a multiplication, so the source decides
Consider a sensor with 1 MΩ of source resistance driving a non-inverting amplifier. The bias current for the non-inverting input has to come through that 1 MΩ, and the voltage it develops appears in series with the signal.
With a bipolar amplifier at IB = 10 nA:
error = IB × Rs = 10 nA × 1 MΩ = 10 mVTen millivolts, referred to the input. Set that against the 150 µV offset from the last lesson and the bias term is nearly 70 times larger. It will also be multiplied by the same noise gain on its way to the output.
With a CMOS amplifier at IB = 1 pA:
error = 1 pA × 1 MΩ = 1 µVOne microvolt, which against a converter code worth 6.8 µV at the input is negligible. Same circuit, same source, same sensor, four orders of magnitude of difference in the error, decided entirely by which amplifier you reached for.
But check it hot. If that 1 pA doubles every 10 °C, then at 85 °C it has doubled six times:
IB(85 °C) ≈ 1 pA × 2⁶ = 64 pA
error = 64 pA × 1 MΩ = 64 µVStill small, but no longer invisible: about nine converter codes at the input. A room-temperature datasheet reading would have told you the wrong story.
Bias current and offset current are not the same number
The two input terminals do not draw exactly the same current. Datasheets describe this with two parameters:
- Input bias current (IB) is the average of the two, and it is what flows
through each input's external resistance.
- Input offset current (IOS) is the difference between them, and it is
typically a small fraction of IB.
The distinction has a practical payoff. If both inputs see the same external resistance, the two bias currents develop nearly equal voltages, and the differential amplifier rejects what they have in common. What survives is the mismatch acting on that resistance, which is IOS rather than IB.
For our bipolar case, suppose IOS is 1 nA against IB of 10 nA. Adding a resistor on the other input to match 1 MΩ changes the error from:
IB × Rs = 10 nA × 1 MΩ = 10 mVto:
IOS × Rs = 1 nA × 1 MΩ = 1 mVA factor of ten, from one resistor. That is a real technique, and it has a real cost.
What balancing costs you
The balancing resistor is a resistor, and resistors make noise. A 1 MΩ resistor at room temperature produces a thermal noise density of about:
en = √(4kTR) = √(4 × 1.38×10⁻²³ × 298 × 10⁶) ≈ 128 nV/√HzOver a 10 kHz bandwidth that is 128 nV/√Hz × √10 000 ≈ 12.8 µV rms, which is around two converter codes of noise added at the input in exchange for removing nine codes of DC error. In this example that is a good trade. In a wider-bandwidth circuit it might not be, and the point is that it is a trade rather than a free improvement.
The usual mitigation is to bypass the balancing resistor with a capacitor, so it presents its full resistance to DC and much less to the noise bandwidth. That works, and it introduces a time constant that has to be compatible with how fast the circuit needs to respond.
Balancing also assumes the bias currents flow in the same direction and are genuinely correlated. In parts with internal bias-current cancellation they may not be, and matching the resistances can make the error worse rather than better. Where that is the case the datasheet usually says so.
Choosing an input technology
| Bipolar | CMOS or JFET | |
|---|---|---|
| Typical bias current | nanoamps to microamps | picoamps |
| Behaviour with temperature | relatively flat | roughly doubles every 10 °C |
| Best with source resistance | low to moderate | high |
| Typical voltage noise | lower | higher |
| Typical initial offset | often tighter | often looser |
| Does resistor balancing help? | usually | not meaningfully, the error is already tiny |
Read that as a pair of questions rather than a verdict. What is the source resistance, and over what temperature range? High impedance at high temperature is the case that needs the most care, because it is the one where both the leakage and the resistance are working against you.
The failure mode everyone meets once
Bias current has to come from somewhere. An input that is AC-coupled through a capacitor, with no resistive path to a DC reference, gives it nowhere to go. The current charges the capacitor, the input drifts, and the output ends up against a rail for reasons that look completely mysterious until you remember that the input needed a DC return.
The fix is a resistor to the reference node, sized against the bias current and the error it produces, which is exactly the calculation above.
What comes next
Lesson 7 moves from how much current the inputs draw to where the inputs are allowed to sit. It is the limit that produces wrong answers while the output is still comfortably inside its range.
Sources and further reading
- Texas Instruments: Trade-offs Between CMOS, JFET, and Bipolar Input Stage Technology (SBOA355) — application report, where the input current comes from in each technology and how it behaves with temperature.
- Texas Instruments: AN-20 An Applications Guide for Op Amps (SNOA621) — application report, bias current as a circuit error term and the resistance that converts it.
- Microchip: AN1747 Operational Amplifier Applications Using 8-Bit PIC Microcontrollers — application note, bias current across source impedance and the resulting offset.
- Microchip: AN722 Operational Amplifier Topologies and DC Specifications — application note, bias current and offset current as separate specifications.