PCB Release Checklist: 20 Things to Verify Before Production

What this checklist is for

Twenty checks to work through before a board goes to production. None of them is clever. All of them catch errors that are cheap to find now and expensive to find at the assembler.

Work through it as a list, not from memory. The value is in the boring items you would have skipped.

Adapt it. If your fabricator never asks for impedance, drop that line. If you build variants, add two. A checklist nobody tailors is a checklist nobody uses.

Design

1. The schematic is annotated, with no duplicate designators. Two parts sharing a designator means the BOM, the layout and the placement file disagree about what exists.

2. ERC has been run and every warning has been read. Not cleared — read. Suppressing a warning is a decision; ignoring it is not.

3. The layout has been updated from the schematic since the last change. The single most common cause of a BOM that does not match the board.

4. DRC passes with your fabricator's constraints, not the defaults. Minimum trace, clearance, annular ring, drill sizes. From the supplier you are actually using.

5. Every footprint has been checked against its datasheet. At least for parts you have not used before. A wrong land pattern is found at assembly, which is the worst place.

6. Polarity and pin 1 are marked on the silkscreen. And they survive soldermask — a pin 1 dot under a pad is not a marking.

BOM

7. Every line has a manufacturer and an MPN. "10k 0603" cannot be bought by someone who is not you.

8. DNP lines are present, marked and explained. Deleted DNP lines are how empty footprints get populated.

9. Quantities match the designator counts. A line listing C12–C18 with quantity 6 is wrong, and nothing will tell you.

10. Lifecycle checked for the parts that matter. Processors, regulators, connectors, anything single-sourced. Not all 142 lines.

11. Approved alternatives are listed where they exist. And the lines with deliberately no alternative say so, with the reason.

Manufacturing files

12. The Gerber layer count matches the stackup. Count them. Both directions — missing layers and extra ones.

13. There is exactly one closed board outline, on one layer. The most common cause of a fabrication delay.

14. Drill files are present, and the drawing states finished vs tooling size. One line in the notes. Prevents holes that are the wrong size.

15. The Gerbers have been opened in an independent viewer. Not the tool that generated them. Five minutes, catches the layer you forgot.

16. The centroid origin matches the Gerber origin. Otherwise every part is placed offset by the same amount.

17. DNP parts are not in the centroid file. Cross-check the designator lists against the BOM. Two minutes.

18. The rotation convention is agreed with the assembler, in writing. Rotation is not standardised. A connector at 180° scraps the build.

Control

19. The board revision is stated inside the files, not only in the ZIP name. File names get renamed, copied and duplicated. Data does not.

20. Someone other than the author has reviewed the package. Not a full design review — twenty minutes with this list. The author cannot see their own assumptions, which is exactly what this check is for.

A worked example of check 17

The one check most likely to find something today. From the fictional ORION CONTROL UNIT, Main Control Board rev C.

BOM designators      (142 lines, 4 marked DNP)
  R7   DNP
  C19  DNP
  J4   DNP
  TP3  DNP

Centroid designators (140 rows)
  ... R7 present ✗

R7 is marked DNP on the BOM and still has a row in the centroid. The machine will place it. The board will work on the bench, behave as the wrong variant, and fail in integration.

Cause: the part was marked DNP in the schematic after the last position export. Nothing in the tool flagged it.

What this checklist deliberately does not cover

Design review. Whether the circuit is correct is a different activity with different people. This list assumes the design is right and checks that the package describes it. Test coverage. Whether you can test what you built. * Supply chain. Whether the parts can be bought in the quantity you need, in time.

All three matter. None belongs on a release checklist, because mixing them produces a list so long that nobody completes it.

Using it more than once

A checklist used once is a document. Used every release, it becomes a record: you can tell which releases were checked and by whom, and that turns out to be the useful part when a batch comes back faulty.

Keep the completed list with the release package. It costs nothing and it is the only evidence that step 20 actually happened.

Running the checks is twenty minutes. Knowing, eighteen months later, which version of the package passed them — and which boards were built from it — is the part that needs somewhere to live.

In XKEMA a manufacturing package belongs to a PCB revision, and an approved version is frozen with a verifiable record of what was approved.

Hardware revision control PCB manufacturing package checklist * What gets frozen when you release a board?